Process–architecture–optimization model
part 3/4 · 6.4 KB total
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See also
• Template:Intel processor roadmap
Notes
cite-note-101. Cannon Lake: only 1 CPU released, microarchitecture dumped 1.5 year later.
References
cite-note-anandtech-10nm-delay-11. ↑ Tick Tock On The Rocks: Intel Delays 10nm, Adds 3rd Gen 14nm Core Product "Kaby Lake". AnandTech. 16 July 2015.
cite-note-22. ↑ citerefcutressCutress, Ian. "Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'". Archived from the original on March 23, 2016.
cite-note-eteknix-pao-33. ↑ citerefeteknix-com2016eTeknix.com (23 March 2016). "Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix".
cite-note-44. ↑ "Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews". 23 March 2016.
cite-note-55. ↑ "Intel 7th Gen Core: Process Architecture Optimization". 30 August 2016.
cite-note-anandtech-kaby-lake-release-62. Intel Launches 7th Generation Kaby Lake: 15W/28W with Iris, 35-91W Desktop and Mobile Xeon - 03 January 2017.
cite-note-73. citerefcutressCutress, Dr Ian. "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm". www.anandtech.com. Archived from the original on December 11, 2019. Retrieved 2021-03-15.
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